Power amplifiers are often provided at a front end of a microwave communication system, for providing high output power. Limited by the rated breakdown voltage and operating current of transistors, the power amplifiers usually have to include a plurality of transistors so as to increase the operating voltage and current of the power amplifiers.
“Microwave Transistor Amplifiers, Analysis and Design, 2nd edition” (Chapter 3, Upper Saddle River, N.J.: Prentice Hall, 1997, Guillermo Gonzalez) discloses a power amplifier having a plurality of transistors. The transistors have input ends connected in parallel with each other, and output ends connected in parallel with each other. As such, the input ends of the transistors have the same potential and current, and the output ends of the transistors also have the same potential and current. However, since these transistors are connected in parallel with each other, currents flowing through the power amplifier are inevitably large, thereby causing a large line loss. Moreover, the input and output impedances of the power amplifier are very small, thus making the design of the power amplifier more challenging and difficult.
U.S. Pat. Nos. 6,888,396 and 5,867,061 disclose another power amplifier having a plurality of transistors. Although the input ends of this power amplifier are again connected in parallel with each other, this configuration is different from the above in that the output ends are now combined in series. Accordingly, the currents coming out of the output ends of the power amplifier remain the same, but the voltage is increased, thus achieving good power combination efficiency. However, since the input ends of the power amplifier are still combined in parallel with each other, the input impedance thereof is still too small to allow easy designing. In addition, “Transformer coupled stacked FET power amplifier” (IEEE Journal of Solid State Circuits, vol. 34, no. 2, pp. 157-161, February 1999, John G. Mcrory, Gordon G. RabJohn, and Ronald H. Johnston), “Fully integrated CMOS power amplifier design using the distributed active transformer architecture” (vol. 37, issue 3, pp. 371-383, March 2002, I. Aoki, S. D. Kee, D. B. Rutledge, A. Hajimiri), “A 2.4-GHz, 2.2-W, 2-V fully-integrated CMOS circular-geometry active-transformer power amplifier” (IEEE conference on Custom Integrated Circuits 2001, pp. 215-218, I. Aoki, S. D. Kee, D, Rutledge, A. Hajimiri), and U.S. Pat. Nos. 6,816,012 and 6,856,199 also disclose similar power amplifiers.
“A new power amplifier topology with series biasing and power combining of transistors” (1992 IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium Digest, pp. 39-41, 1-3 Jun. 1992, M. Shifrin, Y. Ayasli and P. Katzin) and “The high voltage/high power FET” (IEEE RFIC Symp. Dig., 2003, pp. 215-218, A. K. Ezzeddine and H. C. Huang) disclose yet another power amplifier. The output ends of this power amplifier are also combined in series. However, the input ends of this power amplifier are designed such that all the powers are applied to the first transistor. Although such power amplifier may have large input impedance, the parasitic effect of the transistors cannot be neglected when the power amplifier is operating in a high frequency. As a result, the power combination efficiency of such power amplifier is greatly reduced.